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pci-express gen 2 & gen 3 clo ck generator & fan-out buffer with eproclock ? technology SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 1 of 13 400 west cesar chavez, austin, tx 78701 1+( 512) 416-8500 1+(512) 416-9669 www.silabs.com features ? pci-express gen 2 & gen 3 compliant ? low power push-pull type differential output buffers ? integrated resistors on differential clocks ? hw selectable buffered input or crystal synthesizer mode ? dedicated output enable pin for all clocks ? hw selectable frequency and spread control ? four pci-express gen2 & gen 3 clocks ? 25mhz crystal input or clock input ? eproclock ? programmable technology ?i 2 c support with readback capabilities ? triangular spread spectrum profile for maximum electromagnetic interference (emi) reduction ? industrial temperature -40 o c to 85 o c ? 3.3v power supply ? 32-pin qfn package block diagram pin configuration * internal 100k-ohm pull-upresistor ** internal 100k-ohm pull-down resistor pll 1 (ssc) logic core divider sclk sdata src [3:0] xin xout oe_src [3:0] eproclock technology vr ss [1:0] crystal/ clkin pd# in_sel diffin diffin#
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 2 of 13 32-qfn pin definitions pin no. name type description 1 vdd pwr 3.3v power supply 2 ss0** i, pd freqency/spread co ntrol. default ss[1:0] =00. (internal 100k-ohm pull-down) 3 ss1** i, pd 4 in_sel* i, pu 3.3v input to select between crystal input or external differential buffer input mode. 0 = synthesizer mode, 1=fan-out buffer mode (internal 100k-ohm pull-up; switching is not glitchless) 5 vss gnd ground 6 oe_src0* i,pu 3.3v input to enabled src0 clock. (internal 100k-ohm pull-up) 7 oe_src1* i,pu 3.3v input to enabled src1 clock. (internal 100k-ohm pull-up) 8 vdd pwr 3.3v power supply 9 oe_src2* i,pu 3.3v input to enabled src2 clock. (internal 100k-ohm pull-up) 10 vss gnd ground 11 src0 o, dif 100mhz true differential serial reference clock 12 src0# o, dif 100mhz complement differential serial reference clock 13 src1 o, dif 100mhz true differential serial reference clock 14 src1# o, dif 100mhz complement differential serial reference clock 15 vdd pwr 3.3v power supply 16 vss gnd ground 17 src2# o, dif 100mhz complement differential serial reference clock 18 src2 o, dif 100mhz true differential serial reference clock 19 src3# o, dif 100mhz complement differential serial reference clock 20 src3 o, dif 100mhz true differential serial reference clock 21 vss gnd ground 22 vdd pwr 3.3v power supply 23 oe_src3* i,pu 3.3v input to enabled src3 clock. (internal 100k-ohm pull-up) 24 sclk i smbus compatible sclock 25 sdata i/o smbus compatible sdata 26 ckpwrgd/pd#* i,pu 3.3v lvttl input. this pin is a level sensitive strobe used to latch the ss[1:0]. after ckpwrgd (active high) assertion, this pin becomes a real-time input for asserting power down (active low) 27 vdd pwr 3.3v power supply 28 xout o 25.00mhz crystal output, float xout if using only clkin (clock input) 29 xin / clkin i 25.00mhz crystal input or 3.3v, 25mhz clock input 30 diffin i true differential serial reference clock input 31 diffin# i complement differential serial reference clock 32 vss gnd ground ss1 ss0 frequency spread note 0 0 100m off default 0 1 100m -0.5% 1 0 100m -/+0.25 1 1 100m -0.75% mid 0 125mhz off mid 1 200mhz off
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 3 of 13 eproclock ? programmable technology eproclock ? is the world?s first non-volatile programmable clock. the eproclock ? technology allows board designer to promptly achieve optimum compliance and clock signal integrity; historically, attainable typically through device and/or board redesigns. eproclock ? technology can be configured through smbus or hard coded. features: - > 4000 bits of configurations - can be configured through smbus or hard coded - custom frequency sets - differential skew control on true or compliment or both - differential duty cycle control on true or compliment or both - differential amplitude control - differential and single-ended slew rate control - program internal or external series resistor on single-ended clocks - program different spread profiles - program different spread modulation rate frequency/spread select pin ss[1:0] apply the appropriate logic levels to ss [1:0] inputs before ckpwrgd assertion to achieve clock frequency selection. when the clock chip samp led high on ckpwrgd and indicates that the voltage is stable then ss [1:0] input values are sampled. this process empl oys a one-shot functionality and once the ckpwrgd sampled a valid high, all other ss[1:0], and ckpwrgd transitions are ignored. serial data interface to enhance the flexibility and functi on of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers are individually enabled or disabled. the registers associated with the serial data interface initialize to their default setting at power-up. the use of this interface is optional. clock device register changes are normally made at system initialization, if any ar e required. the interface cannot be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read opera tions from the controller. for block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. for byte write and byte read operations, the system controller can access individually indexed bytes. the offset of the indexed byte is encoded in the command code described in ta ble 1 . the block write and block read protocol is outlined in table 2 while table 3 outlines byte write and byte read protocol. the slave receiver address is 11010010 (d2h). frequency/spread select pin (ss[1:0]) ss1 ss0 frequency (mhz) spread (%) note 0 0 100.00 off default value for ss [1:0] =00 0 1 100.00 - 0.5 1 0 100.00 +/- 0.25 1 1 100.00 - 0.75 mid 0 125 off mid 1 200 off table 1. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte wr ite operation. for block read or block writ e operations, these bits should be '0000000 ' table 2. block read and block write protocol block write protocol block read protocol bit description bit description 1start 1start
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 4 of 13 control registers 8:2 slave address?7 bits 8:2 slave address?7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count?8 bits 20 repeat start 28 acknowledge from slave 27:21 slave address?7 bits 36:29 data byte 1?8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2?8 bits 37:30 byte count from slave?8 bits 46 acknowledge from slave 38 acknowledge .... data byte /slave acknowledges 46:39 data byte 1 from slave?8 bits .... data byte n?8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from slave?8 bits .... stop 56 acknowledge .... data bytes from slave / acknowledge .... data byte n from slave?8 bits .... not acknowledge .... stop table 3. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 8:2 slave address?7 bits 8:2 slave address?7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte?8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address?7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave?8 bits 38 not acknowledge 39 stop table 2. block read and block write protocol (continued) block write protocol block read protocol bit description bit description byte 0: control register 0 bit @pup type name description 7 0 r/w reserved reserved 6 0 r/w reserved reserved
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 5 of 13 5 0 r/w reserved reserved 4 0 r/w reserved reserved 3 0 r/w reserved reserved 2 0 r/w reserved reserved 1 0 r/w reserved reserved 0 0 r/w reserved reserved byte 0: control register 0 byte 1: control register 1 bit @pup type name description 7 0 r/w reserved reserved 6 0 r/w reserved reserved 5 0 r/w reserved reserved 4 0 r/w reserved reserved 3 0 r/w reserved reserved 2 1 r/w src0_oe output enable for src0 0 = output disabled, 1 = output enabled 1 0 r/w reserved reserved 0 1 r/w src1_oe output enable for src1 0 = output disabled, 1 = output enabled byte 2: control register 2 bit @pup type name description 7 1 r/w src2_oe output enable for src2 0 = output disabled, 1 = output enabled 6 1 r/w src3_oe output enable for src3 0 = output disabled, 1 = output enabled 5 0 r/w reserved reserved 4 0 r/w reserved reserved 3 0 r/w reserved reserved 2 0 r/w reserved reserved 1 0 r/w reserved reserved 0 0 r/w reserved reserved byte 3: control register 3 bit @pup type name description 7 0 r rev code bit 3 revision code bit 3 6 0 r rev code bit 2 revision code bit 2 5 0 r rev code bit 1 revision code bit 1 4 0 r rev code bit 0 revision code bit 0 3 1 r vendor id bit 3 vendor id bit 3 2 0 r vendor id bit 2 vendor id bit 2 1 0 r vendor id bit 1 vendor id bit 1 0 0 r vendor id bit 0 vendor id bit 0 byte 4: control register 4 bit @pup type name description
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 6 of 13 oe[3:0] assertion all differential outputs that were stopped are to resume normal operation in a glitch-free manner. the maximum latency from the assertion to active outputs is between 2 and 6 clocks of the internal reference clock with all differential outputs resuming simultaneously. all stopped differential outputs must be driven high within 10 ns of oe deassertion to a voltage greater than 200 mv. oe[3:0] deassertion the impact of deasserting the oe pins is that all src outputs that are set in the control registers to stoppable via deassertion of oe are to be stopped after t heir next transition. the final state of all stopped src clocks is low/low. pd# (power down) clarification the ckpwrgd/pd# pin is a dual-function pin. during initial power up, the pin functions as ckpwrgd. once ckpwrgd has been sampled high by the clock chip, the pin assumes pd# functionality. the pd# pin is an asynchronous active low input used to s hut off all clocks cle anly before shutting off power to the device. this signal is synchronized internally to the device before powering down the clock synthesizer. pd# is also an asynchronous input for powering up the system. when pd# is asserted low, clocks are driven to a low value and held before turning off the vcos and the crystal oscillator. pd# (power down) assertion when pd# has been sampled low by the internal reference clock all differential clocks will be stopped in a glitch-free mannter to the low-low state wi thin their next two consec- utive rising edges. pd# deassertion the power up latency will be less than 2ms for crystal input reference and less than 8ms for differential input reference clock. this is the delay from the power supply reaching the minimum value specified in the datasheet, until the time that the part is ready to sample any latched inputs on the first rising edge of clkpwrgd. after the first rising edge on the ckpwrgd this pin becmoes pd#. after a valid rising edge on ckpwrgd/pd# pin, a time of not more than 1.8ms is allowed for the clock device?s internal pll?s to power up and lock. after this time, all outputs are enabled in a glitch-free manner within a few clock cycles of each clock. . . . 7 0 r/w bc7 byte count register for block read operation. the default value for byte count is 7. in order to read beyond byte 7, the user should change the byte count limit.to or beyo nd the byte that is desired to be read. 6 0 r/w bc6 5 0 r/w bc5 4 0 r/w bc4 3 0 r/w bc3 2 1 r/w bc2 1 1 r/w bc1 0 1 r/w bc0 byte 4: control register 4 byte 5: control register 5 bit @pup type name description 7 1 r/w reserved reserved 6 1 r/w src_amp2 src am plitude adjustment 000= 300mv, 001=400mv, 010=500mv, 011= 600mv 100= 700mv, 101=800mv, 110=900mv, 111= 1000mv 50r/w src_amp1 41r/w src_amp0 3 1 r/w reserved reserved 2 0 r/w reserved reserved 1 0 r/w reserved reserved 0 0 r/w reserved reserved
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 7 of 13 absolute maximum conditions parameter description condition min. max. unit v dd_3.3v main supply voltage functional ? 4.6 v v in input voltage relative to v ss ?0.5 4.6 v dc t s temperature, storage non-functional ?65 150 c t a industrial temperature, operating ambient functional ?40 85 c t a commercial temperature, operating ambient functional 0 85 c t j temperature, junction functional ? 150 c ? jc dissipation, junction to case jedec (jesd 51) ? 20 c/ w ? ja dissipation, junction to ambient jedec (jesd 51) ? 60 c/ w esd hbm esd protection (human body model) jedec (jesd 22 - a114) 2000 ? v ul-94 flammability rating ul (class) v?0 multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. dc electrical specifications parameter description c ondition min. max. unit vdd core 3.3v operating voltage 3.3 5% 3.135 3.465 v v ih 3.3v input high voltage (se) 2.0 v dd + 0.3 v v il 3.3v input low voltage (se) v ss ? 0.3 0.8 v v ihi2c input high voltage sdata, sclk 2.2 ? v v ili2c input low voltage sdata, sclk ? 1.0 v v ih_ss[1:0]_high ss input high voltage 0.7 vdd+0.3 v v ih_ss[1:0]_mid ss input midvoltage 0.7 1.5 v v il_ss[1:0]_low ss input low voltage v ss ? 0.3 0.35 v i ih input high leakage current except internal pull-down resistors, 0 < v in < v dd ?5 ? a i il input low leakage current except internal pull-up resistors, 0 < v in < v dd ?5 ? ? a v oh 3.3v output high voltage (se) i oh = ?1 ma 2.4 ? v v ol 3.3v output low voltage (se) i ol = 1 ma ? 0.4 v i oz high-impedance output current ?10 10 ? a c in input pin capacitance 1.5 5 pf c out output pin capacitance 6 pf l in pin inductance ? 7 nh idd_ pd power down current ? 1 ma i dd_3.3v dynamic supply current in synthesizer mode differential clocks with 5? traces and 2pf load, frequency at 100mhz. ?50ma i dd_3.3v dynamic supply current in fanout mode differential clocks with 5? traces and 2pf load, frequency at 100mhz. ?30ma
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 8 of 13 ac electrical specifications parameter description condition min. max. unit crystal l acc long-term accuracy measured at vdd/2 differential ? 250 ppm clock input t dc clkin duty cycle measured at vdd/2 47 53 % t r /t f clkin rise and fall times measured between 0.2v dd and 0.8v dd 0.5 4.0 v/ns t ccj clkin cycle to cycle jitter (syt hesizer) measured at vdd/2 ? 250 ps t ltj clkin long term jitter measured at vdd/2 ? 350 ps v ih input high voltage xin / clkin pin 2 vdd+0.3 v v il input low voltage xin / clkin pin ? 0.8 v i ih input highcurrent xin / clkin pin, vin = vdd ? 35 ua i il input lowcurrent xin / clkin pin, 0 < vin <0.8 ?35 ? ua src at 0.7v t dc duty cycle measured at 0v differential 45 55 % rms gen1 output pcie* gen1 refclk phase jitter ber = 1e-12 (including pll bw 8 - 16 mhz, = 0.54, td=10 ns, ftrk=1.5 mhz) 0108ps rms gen2 output pcie* gen2 refclk phase jitter includes pll bw 8 - 16 mhz, jitter peaking = 3db, = 0.54, td=10 ns), low band, f < 1.5mhz 03.0ps rms gen2 output pcie* gen2 refclk phase jitter includes pll bw 8 - 16 mhz, jitter peaking = 3db, = 0.54, td=10 ns), low band, f < 1.5mhz 03.1ps rms gen3 output phase jitter impact ? pcie* gen3 includes pll bw 2 - 4 mhz, cdr = 10mhz) 01.0ps t ccj cycle to cycle jitter measured at 0v differential ? 85 ps t ccj additive cycle to cycle jitter in buffer mode. measured at 0v differential ?50ps l acc long-term accuracy measured at 0v differential ? 100 ppm t r / t f rising/falling slew rate measured differentially from 150 mv 2.5 8 v/ns v ox crossing point voltage at 0.7v swing 300 550 mv enable/disable and set-up t stable clock stabilization from power-up ? 1.8 ms t ss stopclock set-up time 10.0 ? ns
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 9 of 13 test and measurement set-up for differential clock signals this diagram shows the test load configur ation for the differential clock signals figure 1. 0.7v differential load configuration figure 2. differential measurement for differentia l output signals (for ac parameters measurement)
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 10 of 13 figure 3. single-ended measurement for differentia l output signals (for ac parameters measurement)
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 11 of 13 ordering information part number package type product flow lead-free SL28PCIE14alc 32-pin qfn commercial, 0 ? to 85 ? c SL28PCIE14alct 32-pin qfn ? tape and reel commercial, 0 ? to 85 ? c SL28PCIE14ali 32-pin qfn industrial, -40 ? to 85 ? c SL28PCIE14alit 32-pin qfn ? tape and reel industrial, -40 ? to 85 ? c package diagrams 32-lead qfn 5x 5mm
SL28PCIE14 doc#: sp-ap-0014 (rev. 0.2) page 12 of 13 document history page document title: SL28PCIE14 pc pci-express gen 2 & gen 3 clock generator & fan-out buffer with eproclock ? technology doc#: sp-ap-0014 (rev. 0.2) rev. ecr# issue date orig. of change description of change aa 1695 02/09/11 jma initial release
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